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EM78M612
Universal Serial Bus Microcontroller Series
EM78M612
Universal Serial Bus Microcontroller V1.1
Specification Revision History Version
1.0 * Initial Version * Correction for some text in General DescriptionP2,rom size 12K2K * Correction for Pin Configuration of EM78M612XBPP5 * ADC Converter Channel Selector Table fixedP16,CH1 Reserved 1.1 * Added PDA Register DescriptionP20,IOC9 * Correction for EEPROM Function DescriptionP24 * Changes made to PDA Function DescriptionP29-32 * Revised ADC Converter ready bit for ADC OperationP17,P34,RAS[7] 2004/04/28
Content
Update
2003/03/05
This specification may change without further notice.
2004/4/28 V1.1
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EM78M612
Universal Serial Bus Microcontroller Series
SPECIFICATION 1 General Description
The EM78M612 is a series of Universal Serial Bus 8-bit RISC Multi-Time Programming (MTP) microcontrollers. It is specifically designed for USB low speed device application and to support legacy device such as PS/2 mouse. The EM78M612 also support one device address and two endpoints. With no firmware involved, these series of microcontrollers can automatically identify and decode Standard USB Command to EndPoint Zero. The EM78M612 is implemented on a RISC architecture. It has five-level stack and eight interrupt sources. The amount of General Input/Output pins is up to 15. Each device has 112 bytes SRAM and is embedded with 4 bytes of E2PROM. The ROM size of the EM78M612 is 2K. These series of chips have special features that accommodate your needs. These features are: Dual Clock mode which allows the device to run on very low power saving frequency Pattern Detecting Application function which is used in a serial transmission to count waveform width Width Modulation that can generate a duty-cycle-programmable signal AD converter with up to 10 bits resolution.
2 Features
Low-cost solution for low-speed USB devices, such as mouse, joystick, and gamepad. USB Specification Compliance Universal Serial Bus Specification Version 1.1 USB Device Class Definition for Human Interface Device (HID), Firmware Specification Version 1.1 Support 1 device address and 2 endpoints USB Application USB protocol handling USB device state handling Identifies and decodes Standard USB commands to EndPoint Zero PS/2 Application Support Auto-detects PS/2 or USB port Built-in PS/2 port interface This specification may change without further notice. 2004/4/28 V1.1 2
EM78M612
Universal Serial Bus Microcontroller Series
Built-in 8-bit RISC MCU 5 level stacks for subroutine and interrupt 8 available interrupts 8-bit real time clock/counter (TCC) with overflow interrupt Built-in RC oscillator free running for WatchDog Timer and Dual clock mode Two independent programmable prescalers for WDT and TCC Two methods of power saving: 1. Power-down mode (SLEEP mode) 2. Low frequency mode. Two clocks per instruction cycle Multi-time programmable I/O Ports Up to 15 general purposes I/O pins grouped into two ports (Port 6 and 7). Up to 2 LED sink pins Each GPIO pin of Ports 6 has an internal programmable pull-high resistor (200K Ohms) Each GPIO pin wakes up the MCU from sleep mode by input state change Internal Memory Built-in 2048K*13 bits Program ROM Built-in 112 bytes general purpose registers (SRAM) Built-in USB Application FIFOs. Built-in 4 bytes E2PROM (EM78M612B, EM78M612D) Operation Frequency Normal Mode: MCU runs on the external oscillator frequency Dual Clock Mode: MCU runs at the frequency of 256KHz (or 32KHz, 4KHz, 500Hz), emitted by the internal oscillator with the external ceramic resonator (or crystal) turned off to save power. Built-in Pattern Detecting Application for serial signal transmission Built-in Pulse Width Modulation (PWM) Up to 2 channels PWM function on P.64 (PWM1) and P.65 (PWM2). Up to 8-bit resolution PWM output Up to 8 selections of duty cycles Built-in 15-Channel Analog-to-Digital Converter (ADC) Built-in AD Converter with 10-bit resolution This specification may change without further notice. 2004/4/28 V1.1 3
EM78M612
Universal Serial Bus Microcontroller Series
4 ADC conversion rates: 256K/128K/64K/32K Built-in 3.3V Voltage Regulator For MCU power supply Pull-up source for the external USB resistor on D-pin. Package Type 16 pin PDIP/SOP (EM78M612(A/B/C/D) A P/M) 18 pin PDIP/SOP (EM78M612(A/B/C/D) B P/M) 20 pin PDIP/SOP (EM78M612(A/B/C/D) C P/M) 20 pin SSOP (EM78M612(A/B/C/D) EM) 24 pin PDIP/SOP (EM78M612(A/B/C/D) D P/M) 24 pin SSOP (EM78M612(A/B/C/D) FM)
3 Type Definition
The EM78M612 series has sereval types of packaging. Each type is divided into 4 modules, namely; original, with E2PROM, with A/D converter, and with both E2PROM and A/D converter. Hence, packaging configuration for each series is defined. The Table 3.1 below summarizes which series of the EM78M612 belong to which module.
Original EM78M612A With E PROM EM78M612B
2
With A/D Converter EM78M612C
With Both EM78M612D
Table 3-1 Packaging Summary of EM78M612 Series IC
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EM78M612
Universal Serial Bus Microcontroller Series
4 Applications
This microcontroller is designed for USB low speed device application or non-USB embedded device. It is also suitable for PS/2 mouse application.
5 Pin Configuration
P60/VPP P61 P62 P63 P70 VSS VNN V3.3V OSCI 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 P60/VPP P64 P65 P71 D+/P50 D-/P51 VDD OSCO P61 P62 P63 P70 P72 VSS VNN V3.3V OSCI 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 P64 P65 P66 P67 P71 P73 D+/P50 D-/P51 VDD OSCO
EM78M612XAP
EM78M612XCP
P60/VPP P61 P62 P60/VPP P61 P62 P63 P70 VSS VNN V3.3V OSCI 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 P64 P65 P66 P67 P71 D+/P50 D-/P51 VDD OSCO P63 P70 P72 P74 P76 VSS VNN V3.3V OSCI
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
P64 P65 P66 P67 P71 P73 P75 P77 D+/P50 D-/P51 VDD OSCO
EM78M612XBP
EM78M612XDP
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EM78M612
Universal Serial Bus Microcontroller Series
6 Pin Description
Symbol OSCI OSCO VNN V3.3V O I/O I I/O Function 6MHz / 12MHz ceramic resonator or crystal input. Return path for 6-MHz / 12MHz ceramic resonator or crystal. Used in programming the on-chip ROM. During normal operation, this pin is connected to Ground. 3.3V DC voltage output from internal regulator. This pin has to be tied to a 4.7F capacitor. P60 functins as an input pin only (no output) For serial signal transmission application, the Pin P60 is used as a serial signal input pin. For detailed usage and function, refer to Section 8.8, Pattern Detecting Application of this Spec. 7 GIOP pins. The pull high resistors (200K Ohms) and pull low resistors (15K Ohm) are selected through pin programming. All Port6 I/O pins are used for AD function. Furthermore,P64 & P65 can also be used for PWM function. Port7 offers up to 8 GIOP pins. The sink current of P70 & P71 are programmable for driving LED. Each pin has pull high resistors (200K Ohm) that can be selected through pin programming. All Port7 I/O pins can be used for AD function. USB Plus data line interface or PS/2 line interface are user-defined through firmware setting. When this pin is used as a PS/2 line interface, it will generate an interrupt when its state changes. USB Minus data line interface or PS/2 line interface are user-defined through firmware setting. When this pin is used as a PS/2 line interface, it will generate an interrupt when its state changes. Connects to the USB power source or to a nominal 5V-power supply. Actual VDD range can vary between 4.4V and 5.2V. Connects to ground. Table 7.1 Pin Descriptions
P60/VPP
I
P61 ~ P67
I/O
P70 ~ P77
I/O
D+ / P50
I/O
D- / P51
I/O
VDD VSS
-
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EM78M612
Universal Serial Bus Microcontroller Series
7 Function Block Diagram
OSCI OSCO
VDD V3.3
D+ D-
R2 (PC)
Built-in RC
Oscillator Timing Control
3.3V Regulator
Transceiver
ROM
Stack1 Stack2 Stack3 Stack4 Stack5
EEPROM
USB Device Controller
Instruction register
Prescaler
Prescaler
R3 (Status)
WDT
TCC
Reset & Sleep & Wake up Control
R AM
WDT Timer
R1 (TCC)
Interrupt Control
R4 (RSR)
ALU
Instruction Decoder
ACC
DATA & CONTROL BUS
PWM
ADC
P60/PDA P61/AD P62/AD P83/AD P64/AD P65/AD P66/AD P67/AD
P70/AD P71/AD P72/AD P73/AD P74/AD P75/AD P76/AD P77/AD
P50/D+ P51/D-
Pattern Detect Application
I/O Port 6
I/O Port 7
I/O Port 5
Figure 7 EM78M612 Series Function Block Diagram
8 Function Description
The EM78M612 memory is organized into 4 spaces, namely; User Program Memory in 2048*13 bits ROM space, Data Memory in 112 bytes SRAM space, and USB Application FIFOs (for EndPoint0 and EndPoint1). Furthermore, several registers are used for special purposes.
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EM78M612
Universal Serial Bus Microcontroller Series 8.1 Program Memory
The program space of the EM78M612 is 2K bytes, and is divided into two pages. Each page is 1K bytes long. After Reset, the 11-bit Program Counter (PC) points to location zero of the program space. It has two interrupt vectors, i.e., Interrupt Vectors at 0x0001 and USB Application Interrupt Vectors at 0x000A. The Interrupt Vector applies to TCC Interrupt, High Pattern Detecting Interrupt, Low Pattern Detecting Interrupt, and Port 5 State Changed Interrupt. The USB Application Interrupt Vector is for USB EndPoint Zero Interrupt, USB Suspend Interrupt, USB Reset interrupt ,and USB Host Resume Interrupt. After an interrupt, the MCU will fetch the next instruction from the corresponding address as illustrated in the following diagram.
After reset
PC
Address
0x0000 0x0001
Reset Vector Interrupt Vector
0x000A
USB Application Interrupt Vector
Page 0
0x03FF 0x0400
Page 1
0x07FF
8.2
Data Memory
The Data Memory has 112 bytes SRAM space. It is also equipped with USB Application FIFO space for USB Application. The Figure 8.1 (next page) shows the organization of the Data Memory Space.
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EM78M612
Universal Serial Bus Microcontroller Series
8.2.1 Special Purpose Registers
When the microcontroller executes instruction, specific registers are invoked for assistance, such as; Status Register which records the calculation status, Port I/O Control Registers which control the I/O pins' direction, etc. The EM78M612 series provides a lot more of other special purpose registers with different functions. There are 23 Special Operation Registers which are located from Address 0x00 to 0x0E in Bank0, and from Address 0x08 to 0x0F in Bank1. On other hand, 17 more Special Control Registers are available to control functions or I/O direction. These are arranged from Address 0x05 to 0x0F in Bank0, and from Address 0x08 to 0x0F in Bank1. Note that Special Control Registers can only be read or written by two instructions; IOR and IOW. To access registers from Bank1, the Special Purpose Registers Bank selector (R3[7]) should be set first.
00 01 02 03 04
R0 R1 R2 R3 R4 (Indirection Addressing Register) (Time Clock / Counter Register) (Program Counter) & Stack (Status Register) (RAM Select Register) CBK0 R5 (Data line I/O Register) R6 (Port 6 I/O Register) R7 (Port 7 I/O Register) R8 (Port6 wakeup pin selection Register) R9 (Port7 wakeup pin selection Register) RA (High Pattern Counter Register) RB (Low Pattern Counter Register) RC (USB Application Status Register) RD (USB FIFO address register) RE (USB FIFO data register) RF (Interrupt Status Register) CBK1 R8S (PWM1 Duty Cycle Register) R9S (PWM2 Duty Cycle Register) RAS (AD Channel Select Register) RBS (AD MSB Data Register RCS (AD LSB Data Register)
05 06 07 08 09 0A 0 B 0C 0 D 0E 0F
08 09 0A 0 B 0C 0 D 0E 0F
CBK0 IOC5 (Port 5 I/O Control Register) IOC6 (Port 6 I/O Control Register) IOC7 (Port 7 I/O Control Register) IOC8 (Sink Curent Control Register) IOC9 (PDA Control Register) IOCA (Operation mode Control Register) IOCB (Port 6 pull low Control Register) IOCC (Port 6 pull high Control Register) IOCD (Port 7 pull high Control Register) IOCE (Special Function Control Register) IOCF (Interrupt Mask Register) CBK1 IOC8S (PWM Control Register)
IOCAS (AD Control Register)
RES (EEPROM MODE SELECT Register)
IOCCS (EEPROM BYTE0) IOCDS (EEPROMBYTE1) IOCES (EEPROMBYTE2) IOCFS (EEPROMBYTE3)
10
General Purpose Register
00 01 10 11
EP0's FIFO EP1's FIFO Data Byte Pointer of EP0 Data Byte Pointer of EP1
1F
B y te 0 B y te 1 B y te 2 B y te 3 B y te 4 B y te 5 B y te 6 B y te 7
20
General Purpose Registers (Bank0)
General Purpose Registers (Bank1)
General Purpose Registers (Bank2)
General Purpose Registers (Bank3)
3F
Fig 8.1 The Organization of EM78M612 Data RAM
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EM78M612
Universal Serial Bus Microcontroller Series
8.2.1.1 Operation Registers in Bank 0
The following introduces each of the Operation Registers under the Special Purpose Registers in Bank 0. These Operation Registers are arranged according to the order of registers' address. Note that some registers are read only, while others are both readable and writable. R0 (Indirect Address Register) Default Value: (0B_0000_0000) R0 is not a physically implemented register. Its major function is to be an indirect address pointer. Any instruction using R0 as a pointer actually accesses the data pointed by the RAM Select Register (R4). R1 (Time / Clock Counter) Default Value: (0B_0000_0000) This register TCC, is an 8-bit timer or counter. It is readable and writable as any other register. After Power-on reset and WatchDog reset, the initial value of this register is 0x00. R2 (Program Counter & Stack) Default Value: (0B_0000_0000) The EM78M612 Program Counter is an 11-bit long register that allows access to 2K bytes of Program Memory. The Program Counter is cleared after Power-on reset or WatchDog reset. The first instruction that is executed after a reset is located at Address 00h.
CALL R3[5] R2[9] ~ R2[0] RET RETL RETI Stack 1 Stack 2 Stack 3 Stack 4 Stack 5
0x0000 Reset Vector 0x0001 Interrupt Vector 0x000A USB Interrupt Vector
Page 0
0x03FF 0x0400 Page 1
0x07FF
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EM78M612
Universal Serial Bus Microcontroller Series
R3 (Status Register) Default Value:(0B_0001_1000)
7 SPRBS 6 5 PS0 4 T 3 P 2 Z 1 DC 0 C
R3 [0] R3 [1] R3 [2] R3 [3]
Carry flag. Auxiliary carry flag. Zero flag. It will be set to 1 when the result of an arithmetic or logic operation is zero. Power down flag. It will be set to 1 during Power-on phase or by "WDTC" command and cleared when the MCU enters into Power down mode. It remains in its previous state after WatchDog Reset. 1: Power-on. 0: Power down Time-out flag. It will be set to 1 during Power-on phase or by "WDTC" command. It is reset to 0 by WDT time-out. 1: WatchDog timer without overflow. 0: WatchDog timer with overflow.
R3 [4]
The various states of Power down flag and Time-out flag at different conditions are shown below:
T 1 1 0 1 1 P 1 1 *P 0 0 Condition Power-on reset WDTC instruction WDT time-out Power down mode Wakeup caused by port change during Power down mode *P: Previous status before WDT reset
R3 [5]
Page selection bit. This bit is used to select a page of program memory (refer to R2, Program Counter).
PS0 0 1 Program Memory Page [Address] Page 0 [0000-03FF] Page 1 [0400-07FF]
R3 [6] R3 [7]
General purpose registers. Special purpose registers bank selector. 1: R8S ~ RFS; IOC8S ~ IOCFS 0: R5 ~ RF; IOC5 ~ IOCF 2004/4/28 V1.1 11
This specification may change without further notice.
EM78M612
Universal Serial Bus Microcontroller Series
R4 (RAM Select Register) Default Value: (0B_0000_0000)
7 BK1 6 BK0 5 Ad5 4 Ad4 3 Ad3 2 Ad2 1 Ad1 0 Ad0
R4 (RAM select register) contains the address of the registers. R4 [0~5] are used to select registers in 0x00h~0x3Fh. The address 0x00~0x1F is common space. After 0x1Fh, SRAM is grouped into four banks. R4 [6,7] are used to select register banks. To select a registers bank, refer to the following examples and the table below: (1) R4=00001100 and R4=01001100 point to the same register 0x0Ch. Since 0x0Ch is in the common space, Bit 6 and Bit 7 are meaningless. (2) R4=10111100 points to the register 0x3C in Bank 2.
R4[7]Bk1 0 0 1 1 R4[6]Bk0 0 1 0 1 RAM Bank # Bank 0 Bank 1 Bank 2 Bank3
R5 (Data Line I/O Register) Default Value: (0B_0000_0000)
7 6 5 4 3 2 1 0
D- or PS/2 D+ or PS/2
R5 [0] D+ line register or PS/2 clock interface register. R5 [1] D- line register or PS/2 data interface register. These two bits are BOTH writable and readable when the MCU is operating under PS/2 mode. But under USB Mode, these two bits cannot be accessed. R5 [2~7] General purpose registers. R6 (Port 6 I/O Register) Default Value: (0B_0000_0000)
7 P67 6 P66 5 P65 4 P64 3 P63 2 P62 1 P61 0 P60
R7 (Port 7 I/O Register) Default Value: (0B_0000_0000)
7 P77 6 P76 5 P75 4 P74 3 P73 2 P72 1 P71 0 P70
R8 (Port 6 Wake-up Pin Selection Register) Default Value: (0B_1111_1111)
7 /Wu87 6 /wu86 5 /Wu85 4 /Wu84 3 /Wu83 2 /Wu82 1 /Wu81 0 /Wu80
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Universal Serial Bus Microcontroller Series
R8 [0 ~ 7] Select which of the Port 6 pins are to be defined to wake-up the MCU from sleep mode. When the state of the selected pins changes during sleep mode, the MCU will wake-up and execute the next instruction automatically. 1: Disable the wake-up function 0: Enable the wake-up function R9 (Port 7 Wake-up Pin Selection Register) Default Value: (0B_1111_1111)
7 /Wu77 6 /Wu76 5 /Wu76 4 /Wu74 3 /Wu73 2 /Wu72 1 /Wu71 0 /Wu70
R9 [0 ~ 7] Select which of the Port 7 pins are to be defined to wake-up the MCU from sleep mode. When the state of the selected pins changes during sleep mode, the MCU will wake-up and execute the next instruction automatically. 1: Disable the wake-up function 0: Enable the wake-up function RA (High Pattern Counter Register) Default Value: (0B_0000_0000)
7 HP.7 6 HP.6 5 HP.5 4 HP.4 3 HP.3 2 HP.2 1 HP.1 0 HP.0
This register is used in pattern detecting application. If this function is disabled (IOCE[2] = 0), the PDA function is disabled. RA register is also used as a general-purpose register. RB (Low Pattern Counter Register) Default Value: (0B_0000_0000)
7 LP.7 6 LP.6 5 LP.5 4 LP.4 3 LP.3 2 LP.2 1 LP.1 0 LP.0
This register is used in pattern detecting application. If this function is disabled (IOCE[2] = 0), the PDA function is disabled. RB register is also used as a general-purpose register. RC (USB Application Status Register) Default Value: (0B_0000_0000)
7 EP0_W 6 EP0_R 5 EP1_R 4 0 3 Device_Resume 2 Host_Suspend 1 EP0_Busy 0 Stall
RC [0]
Stall flag. When MCU receives an unsupported command or invalid parameters from host, this bit will be set to 1 by the firmware to notify the UDC to return a STALL handshake. When a successful SETUP transaction is received, this bit is cleared automatically. This bit is both readable and writable. EP0 Busy flag. When this bit is equal to "1," it indicates that the UDC is writing data into the EP0'FIFO or reading data from it. During this time, the firmware will avoid accessing the FIFO until UDC finishes writing or reading. This bit is only readable. 2004/4/28 V1.1 13
RC [1]
This specification may change without further notice.
EM78M612
Universal Serial Bus Microcontroller Series
RC [2]
Host Suspend flag. If this bit is equal to 1, it indicates that USB bus has no traffic for the specified period of 3.0 ms. This bit will also be cleared automatically when a bus activity takes place. This bit is only readable. Device Resume flag. This bit is set by firmware to general a signal to wake-up the USB host and is cleared as soon as the USB Suspend signal becomes low. This bit can only be set by firmware and cleared by the hardware. Undefined Register. The default value is 0.
RC [3]
RC [4]
RC [5,6] EP0_R / EP1_R flag. These two bits inform the UDC to read the data written by firmware from the FIFO. Then the UDC sends the data to the host automatically. After UDC finishes reading the data from the FIFO, this bit is cleared automatically. Therefore, before writing data into the FIFO, the firmware will first check this bit to prevent overwriting the existing data. These two bits can only be set by the firmware and cleared by the hardware. RC [7] EP0_W flag. After the UDC completes writing data to the FIFO, this bit will be set automatically. The firmware will clear it as soon as it gets the data from EP0's FIFO. Only when this bit is cleared that the UDC will be able to write a new data into the FIFO. Therefore, before the firmware can write a data into the FIFO, this bit must first be set by the firmware to prevent UDC from writing data at the same time. This bit is both readable and writable.
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EM78M612
Universal Serial Bus Microcontroller Series
RD (USB Application FIFO Address Register) Default Value: (0B_0000_0000)
7 0 6 0 5 0 4 UAD4 3 UAD3 2 UAD2 1 UAD1 0 UAD0
RD [0~4] RD [5~7]
USB Application FIFO address registers. These five bits are the address pointer of USB Application FIFO. Undefined registers. The default value is zero.
RE (USB Application FIFO Data Register) Default Value: (0B_0000_0000)
7 UD7 6 UD6 5 UD5 4 UD4 3 UD3 2 UD2 1 UD1 0 UD0
RE (USB Application FIFO data register) contains the data in the register of which address is pointed by RD. RF (Interrupt Status Register ) Default Value: (0B_0000_0000)
7 Low Signal_IF 6 High Signal_IF 5 4 3 USB Reset_IF 2 1 0
Port 5 State USB Host Change_IF Resume_IF
USB Suspend_IF EP0_IF TCC_IF
RF [0] RF [1] RF [2] RF [3] RF [4] RF [5] RF [6, 7]
TCC Overflow interrupt flag. It will be set while TCC overflows, and is cleared by the firmware. EndPoint Zero interrupt flag. It will be set when the EM78M612 receives Vender /Customer Command to EndPoint Zero. This bit is cleared by the firmware. USB Suspend interrupt flag. It will be set when the EM78M612 finds the USB Suspend Signal on USB bus. This bit is cleared by the firmware. USB Reset interrupt flag. It will be set when the host issues the USB Reset signal. USB Host Resume interrupt flag. It is set only under Dual Clock mode when the USB suspend signal becomes low. Port 5 State Change interrupt flag. It is set when the Port 5 state changes. High/Low signal Counter interrupt flag. These two flags are used for pattern detecting application.
R10~R1F are General purpose registers. These registers can be used no matter what Bank Selector is. There are 3 banks(BK0~BK2) R20~R3F General purpose registers, Select by R4 [6 7].
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EM78M612
Universal Serial Bus Microcontroller Series
8.2.1.2 Operation Registers in Bank 1
The special purpose registers for special operation (R8S~RES), are located in Special Purpose Register Bank 1. To access these registers, bank selector (R3[7]) must be set first. These Bank 1 located registers serve special functions, such as; E2PROM, Plus Width Modulation, and Analog to Digital Converter. These registers and special functions are described in details in Sections 8.2.3, 8.9, and 8.10 respectively in this specification. R8S ( PWM1 Duty Cycle Register) Default Value(0B_0000_0000) A specified values keeps the output of PWM1 stay at high in a Period.
R9S ( PWM2 Duty Cycle Register) Default Value(0B_0000_0000) A specified values keeps the output of PWM2 stay at high in a Period.
RAS (AD Channel Select Register)
7 ADC 6 Token_Bit 5 0 4
Default Value(0B_0000_0000)
3 AD3 2 AD2 1 AD1 0 AD0
AD4
RAS [0]~[4]:AD Channel Selector AD4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 AD3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 AD2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 AD1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 AD0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Channel Disable AD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 I/O Port Reserved P61 P62 P63 P64 P65 P66 P67 P70 P71 P72 P73 P74 P75 P76 P77
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Universal Serial Bus Microcontroller Series
RAS [6] RAS [7]
Token_Bit will be latched to high by hardware when USB bus is transferring token packet. This bit reset by firmware only. AD Converter ready flag. 0->1Start AD Converting.(Bit set by Firmware) 1->0 When AD finish Converting and moving digital data into AD Data Register , this bit is Clear by Hardware. P.S.: Hardware enable this function only at AD Channel Selector on the functional I/O port.
RBS (AD MSB Data Register) AD Digital Data MSB 8 bits
7 Bit 9 6 Bit 8 5 Bit 7 4 Bit 6 3 Bit 5 2 Bit 4 1 Bit 3 0 Bit 2
This Register is Read only. RCS (AD LSB Data Register) AD Digital Data LSB 2 bits
7 Bit 1 6 Bit 0 5 4 3 2 1 0 -
This Register is Read only. RES (EEPROM Mode Select Register)
Command Value 0B_0000_0000 0B_0000_0001 0B_0000_0010 0B_0000_0011
Default Value ( 0B_0000_0000)
Action Read Write Erase Disable
Execution Time 1ms 9ms 128ms N.A.
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EM78M612
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8.2.1.3 Control Registers in Bank 0
Special purpose registers for special control purposes are also available. Except for the Accumulator (A), these registers must be read and written by special instructions. One of these registers, CONT, can only be read by the instruction "CONTR" and written by "CONTW" instruction. The remaining special control registers can be read by the instruction "IOR" and written by the instruction "IOW." The following paragraphs only describe the general functions of the control registers. For more detailed description, refer to Sections 8.8 to 8.10 of this spec. A (Accumulator Register) The accumulator is an 8-bit register that holds operands and results of arithmetic calculations. It is not addressable. CONT (Control Register) Default Value: (0B_0011_1111)
7 0 6 /INT 5 TSR2 4 TSR1 3 TSR0 2 PSR2 1 PSR1 0 PSR0
[NOTE] The CONT register can be read by the instruction "CONTR" and written by the instruction "CONTW." CONT [0~2] WatchDog Timer prescaler bits. These three bits are used as the prescaler of WatchDog Timer. CONT [3~5] TCC Timer prescaler bits. The relationship between the prescaler value and these bits are as shown below:
PSR2/TSR2 0 0 0 0 1 1 1 1 PSR1/TSR1 0 0 1 1 0 0 1 1 PSR0/TSR0 0 1 0 1 0 1 0 1 TCC Rate 1: 2 1: 4 1: 8 1: 16 1: 32 1: 64 1: 128 1: 256 WDT Rate 1: 1 1: 2 1: 4 1: 8 1: 16 1: 32 1: 64 1: 128
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Universal Serial Bus Microcontroller Series
CONT [6]
Interrupt enable control bit. This bit toggles Interrupt function between enable and disable. It is set to 1 by the interrupt disable instruction "DISI" and reset by the interrupt enable instructions "ENI" or "RETI." 0: Enable the Interrupt function. 1: Disable the Interrupt function.
CONT [7]
Undefined register. The default value is one.
IOC5 ~IOC7 (I/O Port [Port 5 ~ Port 7] Direction Control Registers Each bit controls the I/O direction of three I/O ports respectively. When these bits are set to 1, the relative I/O pins become input pins. Similarly, the I/O pins becomes outputs when the relative control bits are cleared. 1: Input direction. 0: Output direction. IOC5 (Data Line I/O Control Register) Default Value: (0B_0000_0011)
7 0 6 0 5 0 4 0 3 0 2 0 1 I/O 0 I/O
IOC5 [2~7] Undefined registers. The default value is 0. IOC6 (Port 6 I/O Control Register) Default Value: (0B_1111_1111)
7 P67 6 P66 5 P65 4 P64 3 P63 2 P62 1 P61 0 1
IOC6 [0]
This bit is always 1. This is because P60 can only be used as an input pin.
IOC7 (Port 7 I/O Control Register) Default Value: (0B_1111_1111)
7 P77 6 P76 5 P75 4 P74 3 P73 2 P72 1 P71 0 P70
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IOC8 (Sink Current Control Register) Default Value: (0B_0000_0000)
7 0 6 0 5 Sink1.1 4 Sink1.0 3 0 2 0 1 Sink0.1 0 Sink0.0
IOC8 [0,1][4,5] are P70/P71 sink current control registers. Four levels are offered for selection:
Sink0.1/1.1 0 0 1 1 Sink0.0/1.0 0 1 0 1 Sink Current 3mA10% 6mA10% 12mA10% 30mA10%
The default current after Power-on reset is 3mA. IOC9 (Pattern Detecting Application Control Register) Default Value(0B_0111_0000) 7 0 6 Sample Time.2 5 Sample Time.1 4 Sample Time.0 3 0 2 DB.2 1 DB.1 0 DB.0
IOC9 [0~2] Deboucing control registers. This is used for Pattern Detecting Application. There are seven degrees available to debounce the input signal noise. IOC9 [4~6] Sample time selection registers. This is used for Pattern Detecting Application. The default value is 111. Sample Time.2 0 0 0 0 1 1 1 1 Sample Time.1 0 0 1 1 0 0 1 1 Sample Time.0 0 1 0 1 0 1 0 1 Sample Rate ( Divide the frequency of external oscillator by ) /1 /2 /4 /8 / 16 / 32 / 64 / 128
IOC9[3&7] Undefined register. The default value is Zero.
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IOCA (Operation Mode Control Register) Default Value: (0B_1100_0000)
7 Dual_Frq.1 6 Dual_Frq.0 5 0 4 0 3 0 2 0 1 PS/2 0 USB
IOCA [0,1] These two bits are used to select the operation mode. EM78M612 can auto-detect the type of port device being attached. After identifying the port, the firmware will set these two bits to enter into a proper operation mode. The definition of these two control registers is described in the table below.
IOCA[1] 0 0 1 1 IOCA[0] 0 1 0 1 Operation Mode Detect Mode USB Mode PS/2 Mode USB Test Mode
IOCA [2~5] Undefined registers. The default value is 0. IOCA [6,7] Select the operation frequency in Dual Clock mode. Four frequencies are available and can be chosen as Dual Clock mode for running the MCU program.
Dual_Frq.1 0 0 1 1 Dual_Frq.0 0 1 0 1 Frequency 500Hz 4kHz 32kHz 256kHz
IOCB (Port 6 Pull-Low Control Register) Default Value: (0B_0000_0000)
7 PL67 6 PL66 5 PL65 4 PL64 3 PL63 2 PL62 1 PL61 0 -
IOCB [0~7]
Select whether the 15K Ohm pull-low resistor of Port 6 individual pin is connected or not. 1: Enable the pull-low function. 0: Disable the pull-low function. P60 without Pull low Resistor.
IOCC (Port 6 Pull-High Control Register) Default Value: (0B_0000_0000)
7 PH67 6 PH66 5 PH65 4 PH64 3 PH63 2 PH62 1 PH61 0 -
IOCC [0~7]
Select whether the 200K Ohm pull-high resistor of Port 6 individual pin is connected or not. 2004/4/28 V1.1 21
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1: Enable the pull-high function. 0: Disable the pull-high function. P60 without Pull high Resistor IOCD (Port 7 Pull-High Control Register) Default Value: (0B_0000_0000)
7 PH77 6 PH76 5 PH75 4 PH74 3 PH73 2 PH72 1 PH71 0 PH70
IOCD [0~7]
Select whether the 200K Ohm pull-high resistor of Port 7 individual pin is connected or not. 1: Enable the pull-high function. 0: Disable the pull-high function.
IOCE (Special Function Control Register) Default Value: (0B_1111_0000)
7 /Dual clock 6 /WUE 5 WTE 4 RUN 3 0 2 PDA 1 NA 0 NA
IOCE [2]
Pattern Detecting Application Enable Bit. This bit enables the Pattern Detecting function which is used in the Serial Signal Transmission. When this feature is enabled, P60 becomes a serial input pin allowing one pattern detecting block, a counter, and two comparators to function. 1: enable 0: Disable
IOCE [3] IOCE [4]
Undefined register. The default value is zero. Run bit. This bit can be cleared by the firmware and set during power-on, or by the hardware at the falling edge of wake-up signal. When this bit is cleared, the clock system is disabled and the MCU enters into power down mode. At the transition of wake-up signal from high to low, this bit is set to enable the clock system. 1: Run mode. The EM78M612 is working normally. 0: Sleep mode. The EM78M612 is in power down mode.
IOCE [5]
WatchDog Timer enable bit. The bit disable/enables the WatchDog Timer. 1: Enable WDT. 0: Disable WDT. [NOTE] If the Code Option WTC bit is "0," WDT is always disabled.
IOCE [6]
Enable the wake-up function as triggered by port-change. This bit is set by UDC. 1: Disable the wake-up function. 0: Enable the wake-up function.
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IOCE [7]
Dual clock Control bit. This bit is used to select the frequency of system clock. When this bit is cleared, the MCU will run on very low frequency save power and the UDC will stop working. 1: Selects EM78M612 to run on normal frequency. 0: Selects to run on slow frequency.
IOCF (Interrupt Mask Register)
7 Low Signal_IE 6 5
Default Value: (0B_0000_0000)
4 3 USB Reset_IE 2 USB Suspend_IE 1 EP0_IE 0 TCC_IE
High Port 5 State USB Host Signal _IE Change_IE Resume_IE
IOCF [0~7] TCC / EP0 / USB Suspend / USB Reset / USB Host Resume / Port 5 State Change / High Signal / Low Signal interrupt enable bits. These eight bits respectively control the function of TCC interrupt, EP0 interrupt, USB Suspend interrupt, USB Reset interrupt, USB Host Resume interrupt, Port5 State Change interrupt, High pattern counter interrupt and Low pattern counter interrupt. Individual interrupt is enabled by setting its associated control bit in the IOCF to "1". 1: Enable Interrupt. 0: Disable Interrupt. Only when the global interrupt is enabled by the ENI instruction that the individual interrupt will work. After DISI instruction, any interrupt will not work even if the respective control bits of IOCF are set to 1. The USB Host Resume Interrupt works only under Dual clock mode. This is because when the MCU is under sleep mode, it will be waked up by the UDC Resume signal automatically.
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8.2.1.4 Control Registers in Bank 1
Bank 1 offers more of the special purpose control registers. To write or read these registers, the bank selector (R3[7]) must be initially set to 1. For more detailed description of these registers, refer to Sections 8.8 to 8.10 of this spec. IOC8S (PWM Control Register)
7 PEN2 6 PEN1 5 -
Default Value(0B_0000_0111)
4 3 2 PS2 3 PS1 2 PS0
IOC8S [0~2] PWM Clock Prescaler Fosc = 6MHz (No matter Xtal is 6MHz or 12MHz) PS2 0 0 0 0 1 1 1 1 PS1 0 0 1 1 0 0 1 1 PS0 0 1 0 1 0 1 0 1 Clock(Hz) Fosc/3 Fosc/6 Fosc/12 Fosc/24 Fosc/48 Fosc/96 Fosc/192 Fosc/384 Period/255 0.5us 1us 2us 4us 8us 16us 32us 64us
IOC8S [6] PWM1 Enable Bit 0:Disable 1:Enable IOC8S [7] PWM2 Enable Bit 0:Disable. 1:Enable IOCAS (AD Control Register) Default Value(0B_0000_0000)
7 6 5 4 3 2 1 ADPS1 0 ADPS0
IOCAS [0,1]:AD Clock Prescaler ADPS1 0 0 1 1 ADPS0 0 1 0 1 AD Clock Source RC RC/2 RC/4 RC/8 Conversion Rate 20K 10K 5K 2.5K 2004/4/28 V1.1 24
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8.2.2 USB Application FIFOs
For USB Application, EM78M612 provides an 8-byte First-In-First-Out (FIFO) buffer for each endpoint. The buffer cannot be accessed directly. However, a corresponding Data Byte Pointer register for each endpoint is made available to address the individual byte of the FIFO buffer. The content of the individual byte will map to a special register.
8.2.3 E2PROM
Four bytes of E2PROM are located in the IOCC ~ IOCF of control register Bank 1. The stored data of E2PROM are not erased when the power is off and can be read and rewritten by firmware. In some special case of applications, for example, cordless mouse controller, E2PROM can store important data, such as the cordless mouse's device identification number. A control register, RES (address : 0x0E in Bank1) controls the E2PROM, that is, to read, write, or to erase the data from E2PROM. Writing a command into this register will execute an action to E2PROM. The command value is defined in the following table. Note that there is an execution time lapse for each command. Before writing the next command into the control register, allow enough time for the E2PROM to finish processing the previous command.
Command Value 0B_0000_0000 0B_0000_0001 0B_0000_0010 0B_0000_0011 Action Read Write Erase Disable Execution Time 1ms 9ms 128ms N/A
8.3
I/O Ports
The EM78M612 has up to fifteen General Purposes I/O pins, which are classifies into two port groups; Port 6 and Port 7. Each pin has an internal resistor that can be individually selected by user. Notice that Pin 60 is a input only pin.The following describes the important features of EM78M612 I/O pins.
8.3.1 Programmable Large Current
Port 7 has two pins; P70 and P71 that can drive large current of up to 30mA. The range of driving current is from 3mA to 30mA, which is programmable. Use IOC8 [0,1] and IOC8 [4,5] to control the sink current of P70/P71. The default current is 3mA.
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8.3.2 Wakeup by Port Change Function
Each of the GPIO pins in Port 6 and Port 7 can wakeup the MCU through signal change from input pin. This function is used to wake-up the MCU automatically from sleep mode. It also supports the remote wake-up function for USB application. Any of the Individual pins of Port 6 and Port 7 can be defined to wakeup the MCU by setting their respective bits, R8 and R9.
8.4
USB Application
EM78M612 is specially designed for USB device application and has many powerful functions that help the firmware to free itself from complex situation in various aspects of USB application.
8.4.1 Auto-Detect PS/2 or USB Mode
When the EM78M612 is connected to the bus, it will auto-detect and identify which type of bus (USB or PS/2) it is connected to. The conditions that influence auto-detect function are described below: 1. After a Power-on reset, the initial value of IOCA [0,1] is 0b00. Thus the operation mode is "Detect mode" and the D+ and D- I/O pins are internal pulled high by 200K Ohm to VDD. 2. The firmware checks the state of R5 [0,1]. If the state with which these two bits is 0x00, set the IOCA [0] to "1" to define the "USB mode." Otherwise, set the IOCA [1] to "1," to define "PS/2 mode." 3. When the operation mode is defined as "USB mode," the D- I/O pin is internal pulled high by a 1.5K Ohm resistor to 3.3V, which is output from a built-in regulator. 4. If the operation mode is in "PS/2 mode," both of the PS/2 interface I/O pins are internal pulled high by a 4.7K Ohm resistor to VDD. {NOTE] If the auto-detect function is not used, the firmware should set the operation mode, either in USB mode or PS/2 mode, at the beginning of program. An additional mode, "USB Test Mode" is also available. This mode has no load on D+ and D- I/O pins, and can only be used in USB Application case. Therefore, an external 1.5K Ohm resistor is needed to pull up D- I/O pin to 3.3V. Under "PS/2 mode," both PS/2 pins are programmed to generate an interrupt. After setting the Port 5 State change to Interrupt Enable bit, the MCU will interrupt while the state of these two pins changes.
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8.4.2 USB Device Controller
The USB Device Controller (UDC) built-in in the EM78M612 can interpret the USB Standard Command and response automatically without involving firmware. The embedded Series Interface Engine (SIE) handles the serialization and deserialization of actual USB transmission. Thus, a developer can concentrate his efforts more in perfecting the device actual functions and spend less energy in dealing with USB transaction. The UDC handles and decodes most Standard USB commands defined in the USB Specification Rev1.1. If UDC receives an unsupported command, it will set a flag to notify MCU the receipt of such command. The Standard Commands that EM78M612 supports includes; Clear Feature, Get Configuration, Get Interface, Get Status, Set Address, Set Configuration, Set Feature, and Set Interface. Each time UDC receives a USB command, it writes the command into EP0's FIFO. Only when it receives unsupported command that the UDC will notify the MCU through interrupt. Therefore, EM78M612 is very flexible under USB application because the developer can freely choose the method of decoding the USB command as dictated by different situation.
8.4.3 Device Address and Endpoints
EM78M612 supports one device address, two endpoints, EP0 for control endpoint, and EP1 for interrupt endpoint. Sending data to USB host in EM78M612 is very easy. Just write data into EP's FIFO, then set flag, and the UDC will handle the rest. It will then confirm that the USB host has received the correct data from EM78M612.
8.5
Reset
The EM78M612 provides three types of reset: (1) Power-on Reset, (2) WatchDog Reset, and (3) USB Reset.
8.5.1 Power-On Reset
Power-on Reset occurs when the device is attached to power and a reset signal is initiated. The signal will last until the MCU becomes stable. After a Power-on Reset, the MCU enters into following predetermined states (see below), and then, it is ready to execute the program. a. The program counter is cleared. b. The TCC timer and WatchDog timer are cleared. c. Special registers and Special Control registers are all set to initial value. The MCU also has a low voltage detector that detects low output power condition. Whenever the output voltage of the 3.3V regulator decreases to below 2.2V, a reset signal is set off.
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8.5.2 WatchDog Reset
When the WatchDog timer overflows, it causes the WatchDog to reset. After it resets, the program is executed from the beginning and some registers will be reset. The UDC however, remains unaffected.
8.5.3 USB Reset
When UDC detects a USB Reset signal on USB Bus, it interrupts the MCU, then proceed to perform the specified process that follows.
8.6
Power Saving Mode
The EM78M612 provides two options of power saving modes for energy conservation, i.e., Power Down mode, and Dual Clock mode.
8.6.1 Power Down Mode
The EM78M612 enters into Power Down mode by clearing the RUN register (IOCE[4]). During this mode, the oscillator is turned off and the MCU goes to sleep. It will wake up when signal from USB host is resumed, or when the WatchDog resets, or the input port state changes. If the MCU wakes up when I/O port status changes, I/O port direction should be set at input, then the port state is read. For example: : // Set the Port 6 to input port MOV A , 0XFF IOW PORT6 // Read the state of Port 6 MOV PORT6, PORT6 // Clear the RUN bit IOR 0XE AND A , 0B11101111 IOW 0XE : : If the MCU is awaken by a USB Resume signal, the next instruction will be executed, and one flag, RC[3] will be set to 1.
8.6.2 Dual Clock Mode
The EM78M612 has one internal oscillator for power saving application. Clearing the Bit IOCE [7] will enable the low frequency oscillator. At the same time, the external oscillator will be turned off. Then the MCU will run under very low frequency to conserve power. Four types of frequency are available for selection in setting Bits IOCA [6, 7].
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The USB Host Resume Interrupt can only be used in this mode. If this interrupt is enabled, the MCU will be interrupted when the USB Suspend signal is detected on USB Bus.
8.7
Interrupt
The EM78M612 has two interrupt vectors, one is in 0x0001, and the other is in 0x000A. When an interrupt occurs while the MCU is running, it will jump to the interrupt vector (0x0001 or 0x000A) and execute the instructions sequentially from interrupt vector. RF is the interrupt status register that records the interrupt status in the relative flags/bits. The interrupt condition could be one of the following: 1. TCC Overflow 2. EP0 Interrupt When the Timer Clock / Counter Register (R1) overflows, the status flag RF[0] will be set to 1. Its interrupt vector is 0X0001. When the UDC successfully received a setup transaction from host to EndPoint0, the status flag RF[1] will be set to 1. Its interrupt vector is 0X000A. When UDC detects a USB Suspend signal on USB bus, the status flag RF[2] will be set to 1. Its interrupt vector is 0X000A. When the UDC detects a USB Reset signal on USB bus, the status flag RF[3] will be set to 1. Its interrupt vector is 0X000A. When UDC detects that the USB bus has left the Suspend condition, the status flag RF[4] will be set to 1. Its interrupt vector is 0X000A. When the input signals in Port 5 changes, the status flag RF[5] will be set to 1. Its interrupt vector is 0X0001.
3. USB Suspend 4. USB Reset 5. USB Host Resume
6. Port 5 State Change
7. High Pattern Detecting Interrupt Conditions If the Pattern Detecting Application function is enabled, there will be three conditions with which interruption is generated, and the status flag RF[6] is set to 1, Its interrupt vector is 0X0001. a) P.60 turns to low, and the Pattern Counter value bigger than RA register value. b) P.60 stays at high, and Pattern Counter value equal 0XFF. c) P.60 turns to low and Pattern Counter value bigger than 0XFF.
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8. Low Pattern Counter Interrupt Conditions If the Pattern Detecting Application function is enabled, there will be three conditions with which interruption is generated and the status flag RF[7] is set to 1. Its interrupt vector is 0X0001. a) P.60 turns to high, and Pattern Counter value bigger than RB register value. b) P.60 stays low, and Pattern Counter value equal 0XFF. c) P.60 turns to high, and Pattern Counter value bigger than 0XFF. IOCF is an interrupt mask register which can be set individually bit by bit. While their respective bit is written to 0, the hardware interrupt will inhibit, that is, the EM78M612 will not jump to the interrupt vector to execute instructions. But the interrupt status flags still records the conditions no matter whether the interrupt is masked or not. The interrupt status flags must be cleared by firmware before leaving the interrupt service routine and enabling interrupt. The global interrupt is enabled by the ENI (RETI) instruction and is disabled by the DISI instruction.
8.8
Pattern Detecting Application (PDA)
8.8.1 Function Description
This function is designed for the serial signal transmission, e.g., the transmission between a wireless device and its receiver box. The EM78M612 has a built-in Pattern Detecting Application block that ensures the EM78M612 supports wireless devices, such as receiver box controller for a wireless mouse. Pattern Detecting Application (PDA) can calculate the length of one pattern and interrupt the MCU while the serial signal is transiting from high to low (or vise-versa). Then the MCU reads the length value from a specified register.
8.8.2 Control Register
RA (High Pattern Counter Register) Default Value: (0B_0000_0000)
7 HP.7 6 HP.6 5 HP.5 4 HP.4 3 HP.3 2 HP.2 1 HP.1 0 HP.0
This register is used in pattern detecting application. If this function is disabled (IOCE[2] = 0), the PDA function is disabled. RA register is also used as a general-purpose register.
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RB (Low Pattern Counter Register) Default Value: (0B_0000_0000)
7 LP.7 6 LP.6 5 LP.5 4 LP.4 3 LP.3 2 LP.2 1 LP.1 0 LP.0
This register is used in pattern detecting application. If this function is disabled (IOCE[2] = 0), the PDA function is disabled. RB register is also used as a general-purpose register. IOC9 (Pattern Detecting Application Control Register) Default Value(0B_0111_0000)
7 6 5 4 3 2 1 0
0
Sample Time.2
Sample Time.1
Sample Time.0
0
DB.2
DB.1
DB.0
IOC9 [0~2] Deboucing control registers. This is used for Pattern Detecting Application. There are seven degrees available to debounce the input signal noise. IOC9 [4~6] Sample time selection registers. This is used for Pattern Detecting Application. The default value is 111.
Sample Time.2 0 0 0 0 1 1 1 1
Sample Time.1 0 0 1 1 0 0 1 1
Sample Time.0 0 1 0 1 0 1 0 1
Sample Rate ( Divide the frequency of external oscillator by ) /1 /2 /4 /8 / 16 / 32 / 64 / 128
IOC9[3&7] Undefined register. The default value is Zero.
The PDA includes an enable control bit, an input pin (P60), a prescaler, a Pattern Detecting block, two special register (RA and RB), and two interrupts (high pattern counter interrupt and low pattern counter interrupt). To use this function, the enable control bit, IOCE[2] has to be set first. Otherwise the P60 will just be treated as an input only pin and the RA/RB as general purpose register. As long as the IOCE[2] control bit is set to 1 and the P60 is set as input pin, the Pattern This specification may change without further notice. 2004/4/28 V1.1 31
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Detecting block will start to sample the P60 input signal and measure the high pulse or low pulse width. After detecting the transition of this signal and debouncing, the value of the counter will be loaded into the RA (if the signal is transiting from high to low) or RB (if the signal is transiting from low to high), and the counter is cleared to start counting from zero. Two interrupts are supported individually by RA and RB. After the PDA function is enabled (by setting IOCE[2] to 1), a default value is written to the High Pattern counter register and Low Pattern counter register. Then define the corresponding interrupt enable bits (IOCF[6] and IOCF[7]). When the counter value of one "H" pattern is bigger than the RA default value, then the High Pattern Detecting interrupt will be generated. Similarly, if the counter value of one "L" pattern is bigger than the RB default value, the Low Pattern Detecting interrupt will occur. Then, the EM78M612 will be notified that one successful pattern is received from P60. If these two interrupts are not used, they can be masked. The new counter value of a pattern will still be loaded to the RA and RB. The firmware must be made to poll and determines any changes to the value of these two registers. The sample clock is programmable with 8 frequencies to choose from.
8.9
Pulse Width Modulation (PWM)
8.9.1 Function Description
In PWM mode, both of PWM1 (P64) and PWM2 (P65) produce up to a 8-bit resolution PWM output. PWM output has a duty cycle and keeps the output high. The PWM Period is defined as 0xFF * Timer Counter Clock. The Timer Counter clock source is controlled by Control Register IOC8S. For example; if the Clock source is 1MHz, then the Period will be 255 seconds. Period = 255 * (1/Timer Counter Clock)
Period (0xFF * Clock)
Duty Cycle
Fig.8.9.2 The PWM Output Timing
The PWM duty cycle is defined by writing to the R8S/R9S Register for PWM1/PWM2. Duty Cycle = R8S * (1/Timer Counter Clock) for PWM1 R9S * (1/Timer Counter Clock) for PWM2
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8.9.2 Control Register
R8S (PWM1 Duty Cycle Register) A specified value keeps the output of PWM1 to remain at high within a Period. R9S (PWM2 Duty Cycle Register) A specified value keeps the output of PWM2 to remain at high within a Period. IOC8S (PWM Control Register) Default Value: (0B_0000_0111)
7 PEN2 6 PEN1 5 4 3 2 PS2 1 PS1 0 PS0
IOC8S [0~2] PWM Clock Prescaler. Fosc = 6MHz (No matter Xtal is 6MHz or 12MHz)
PS2 0 0 0 0 1 1 1 1 PS1 0 0 1 1 0 0 1 1 PS0 0 1 0 1 0 1 0 1 Clock(Hz) Fosc/3 Fosc/6 Fosc/12 Fosc/24 Fosc/48 Fosc/96 Fosc/192 Fosc/384 Period/255 0.5us 1us 2us 4us 8us 16us 32us 64us
IOC8S [6,7] PWM1/PWM2 Enable Bit 0:Disable 1:Enable
8.10 Analog-To-Digital Converter (ADC)
8.10.1 Function Description
The Analog to Digital converter consists of a 5-bit analog multiplexer, one Control Register (IOCAS), one AD Channel Select Register (RAS), and two data registers (RBS & RCS) for 10-bit resolution The ADC module utilizes successive approximation to convert the unknown analog signal to a digital value. The result is fed to the ADDATA. Input channels are selected by the analog input multiplexer via the ADCS/RAS bits AD0~AD4.
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10-bit resolution: 0x00-00~0xC0-FF (0b11000000-11111111) Start (0x00-00): Full (0xC0-FF): 0 Vref~(1/1024)*Vref (1023/1024)*Vref~Vref
Conversion Rate: 2.5K; 5K; 10K; & 20K
8.10.2 Control Register
RAS (AD Channel Select Register) Default Value: (0B_0000_0000)
7 ADC 6 Token Bit 5 0 4 AD4 3 AD3 2 AD2 1 AD1 0 AD0
RAS [0~4]:AD Channel Selector
AD4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 AD3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 AD2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 AD1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 AD0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Channel Disable AD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 I/O Port Reserved P61 P62 P63 P64 P65 P66 P67 P70 P71 P72 P73 P74 P75 P76 P77
RAS [6] Token Bit. This bit is asserted when MCU receives or transmits USB transaction. RAS [7] AD Converter ready flag. 0 1 1: Start AD Conversion (Set by firmware). 0: When AD finishes converting and has moved digital data into AD Data Register, this bit will be Cleared by hardware.
[NOTE] Hardware can enable this function only at AD Channel Selector of the functional I/O port. After Power-on reset, the initial value of this register is 0b0000 0000.
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RBS (AD MSB Data Register) Default Value: (0B_0000_0000)
7 Bit 9 6 Bit 8 5 Bit 7 4 Bit 6 3 Bit 5 2 Bit 4 1 Bit 3 0 Bit 2
AD Digital Data MSB 8 bits. RCS (AD LSB Data Register) Default Value: (0B_0000_0000)
7 Bit 1 6 Bit 0 5 0 4 0 3 0 2 0 1 0 0 0
AD Digital Data LSB 2 bits. IOCAS (AD Control Register) Default Value: (0B_0000_0000)
7 0 6 0 5 0 4 0 3 0 2 0 1 ADPS1 0 ADPS0
IOCAS [0,1]: AD conversion rate. 00: 256kHz 01: 128kHz 10: 64kHz 11: 32kHz
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9 Absolute Maximum Ratings
Symbol Temperature under bias Storage temperature Input voltage Output voltage Min 0 -65 -0.5 -0.5 Max 70 150 6.0 6.0 Unit C C V V
10 DC Electrical Characteristic
(T = 0C ~70C, VDD=4.4~5.2V, VSS=0V)
Symble VRag VResetL VResetH IIL VIHX VILX ICC1 Parameter Output voltage of 3.3v Regulator Low Power Reset detecting low Voltage Low Power Reset detecting high Voltage MCU Operation Input Leakage Current for input pins Clock Input High Voltage Clock Input Low Voltage VDD operating supply current - Normal frequency operation mode VDD operating supply current - Normal frequency operation mode Operating supply current 1 - Power down mode Operating supply current 2 - Low frequency mode VIN= VDD,VSS OSCI OSCI Crystal type Freq. = 6MHz Output pins floating Crystal type Freq. = 12MHz Output pins floating All input and I/O pins at VDD Output pins floating WDT disabled RC oscillation type Freq. = 20kHz~50kHz Output pins floating GPIO Pins VIH VIL VOH VOL IPH Input High Voltage Input Low Voltage Output High Voltage (Port5 & Port 6 & P72~P77), OSCO) Output Low Voltage (Port5 & Port 6 & P72~P77, OSCO) Input current with pull-high resister Port 5 Port 5 IDrive = 5.0mA ISink = 5.0mA The input pin with internal pull-high resistor of Port6 or Port7 is connected to VSS. The input pin with internal pull-low resistor of Port6 is connected to VDD. 2.4 25 0.4 V V V V A 2.5 1 1.0 10 A V V mA Condition 3.3V Regulator VDD = 4.2V ~ 5.2V 3.0 3.3 3.6 V V V Min Type Max Unit
ICC2
-
-
20
mA
ISB1
-
-
50
A
ISB2
-
-
200
A
IPL
Input current with pull-low resister
-
330
-
A
This specification may change without further notice.
2004/4/28 V1.1
36
EM78M612
Universal Serial Bus Microcontroller Series
USB Interface VOH VOL VDI VCM VSE CIN VRG IPH Static Output High Static Output Low Differential Input Sensitivity Differential Input Command Mode Range Single Ended Receiver Threshold Transceiver Capacitance Output Voltage of Internal Regulator Input current with pull-high resister (D-) Programmable Large Current ISink1 ISink2 ISink3 ISink4 P70, P71 Output Sink Current P70, P71 Output Sink Current P70, P71 Output Sink Current P70, P71 Output Sink Current VOUT = 0.4V, IOC8[0,1] or IOC8[4,5] = 00 VOUT = 0.4V, IOC8[0,1] or IOC8[4,5] = 01 VOUT = 0.4V, IOC8[0,1] or IOC8[4,5] = 10 VOUT = 0.4V, IOC8[0,1] or IOC8[4,5] = 11 Internal Memory Cycle Time TROM TEE Endurance of Program ROM Endurance of E2PROM T = 25C, Vpp=10V, VNN=-10V T = 25C, VDD = 4.4V ~ 5.25V 1K 4K Cycle Cycle -10% -10% -10% -10% 3 6 12 30 +10% +10% +10% +10% mA mA mA mA USB operation Mode USB operation Mode 2.8 0.2 0.8 0.8 3.0 3.6 0.3 2.5 2.0 20 3.6 V V V V V pF V mA
This specification may change without further notice.
2004/4/28 V1.1
37
EM78M612
Universal Serial Bus Microcontroller Series
(c) 2004 ELAN Microelectronics Corporation All Rights Reserved
Printed in Taiwan, ROC, 04/2004
The contents of this specification are subject to change without notice. ELAN Microelectronics assumes no responsibility for errors that may appear in this specification. ELAN Microelectronics makes no commitment to update, or to keep current, the information contained in this specification. The products described herein are not intended for use in life support appliances, devices, or systems. Use of ELAN Microelectronics products in such applications are not supported and is prohibited. NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY MEANS WITHOUT THE EXPRESS WRITTEN PERMISSION OF ELAN MICROELECTRONICS.
ELAN
MICROELECTRONICS
CORPORATION
Headquarters:
No. 12, Innovation Road 1, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C. Tel: +886 3 5639977 Fax: +886 3 5639966 http://www.emc.com.tw
Hong Kong Office:
Rm. 1005B, 10/F Empire Centre 68 Mody Road, Tsimshatsui Kowloon , HONG KONG Tel: +852 2838-8715 Fax: +852 2838-0497
This specification may change without further notice.
2004/4/28 V1.1
38

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